Lunchtime Talk : Jean Trewhella – Acceleration of Electronic Packaging Innovation through Collaboration

Acceleration of Electronic Packaging Innovation through Collaboration

IEEE CPMT President


photo_trewhella_2010As semiconductor scaling has slowed down making the cost per transistor increase the world has turned to packaging to lead the charge of innovation.   This is evident by the growth in packaging papers published per year at IEEE conferences and workshops. They have increased over 3X in past 20 years with over 3800 publications in 2015 alone!  Packaging innovation papers are not only being seen in the traditional packaging forums sponsored by the IEEE CPMT but they are cropping up in many of the hardware societies.  The CPMT Society recognizes this and we are driving collaboration across societies, and organizations to provide a comprehensive Heterogeneous Integration Roadmap to be used by the industry at large.

Why is packaging growing so rapidly?   We are seeing the demands increasing with the fruition of the Internet of Things (IOT).  All areas of Packaging covered by CPMT will be called on to collaborate to drive the required electronic packaging innovations. The sensors themselves require new materials and reliability solutions meet the challenges of new harsh environments. Compute power and massive storage needs will drive new packaging advances to support localized low cost, low power processors for data analysis as well the other extreme requirements of the highly secure high power central processing hubs. IOT interconnects with their ever increasing bandwidth and latency requirements will call on innovations in signal and power integrity for wired and wireless connections. Assembly manufacturing advances are needed to address a much broader set of components including optical, electronic, actives, passives, and antennas which need to be tightly integrated.  Time to market is key and thus modeling and simulation will be called on to predict the thermal and mechanical resilience of the required hybrid solutions.

As the Packaging Society for IEEE, we welcome you to join CPMT as we strive to support the collaboration of technical communities through the exchange of ideas during this exciting time of exploration!



Ms. Trewhella received her B.S. in Physics from Antioch College (1987) and her M.S. in Applied Physics from Columbia University (1992). She joined the T.J. Watson Research Center, IBM, in 1988 where her work included polymer optical waveguides fabrication, electrical modeling, and opto-mechanical package design for data communication systems. In 2000 she created the High Speed Electrical and Optical Packaging Group in IBM Research directing work in electrical link signal integrity,  advanced 1st and 2nd level packaging, and low cost high speed opto-mechanical packaging. She received an Outstanding Technical Achievement Award for her work on 10Gbps Ethernet Transceiver Development in 2003. In 2005 she drove IBM wide team of engineers and scientists to highlight key disruptive technologies synthesizing the messages into three GTO topics: Technology, Application-Optimized Systems, and Services 2.0.  From 2006-2008 she was responsible for the Electronic Packaging Integration Group in IBM STG where her team developed the power5 and z10 system hardware. Currently Jean Trewhella is the Director of IBM Packaging Research and Development Center with responsibility of 3D, low cost, and high performance packaging technology for current and future products.

Ms. Trewhella was on the Strategic Advisory Board for NSF STC – Materials & Devices for Information Technology Research 2004-2008, she served as the General Chair of the 60th ECTC and is currently a member at large of the CPMT Board of Governors. She has authored numerous papers and holds over 20 US patents.

Series of Hot Topics

EPTC 2016 bring out several hot topics in the industry.


Through Silicon Vias (TSV) technology was adopted in production a few years ago for MEMS and CMOS Image Sensors (CIS). Driven by consumer applications such as smartphones and tablets, this market have grown over the last several years. 3DIC adoption & implementation has been seen for high-end memories (HBM/HBC) from 2014. Standards have now been established, the industry has grown in high-volume manufacturing. Wide I/Os,  logic-on-logic will follow, and Heterogeneous 3DIC nowadays is heating up. EPTC 2016 has lined up short courses on 3DIC integration / 3DIC Packaging & FA methods for 2.5D/3DIC and invited papers / speakers to present on the TSV / 3DIC  integration on Advanced technology node. Full details are in the subsequent pages. Download speaker line up here.



Autonomous driving, Clean & Green and connectivity & entertainment driving the growth of electronics contents in the automotive industry.  Many of the new functions requires new unique packaging requirements.   The new packaging needs extended hours at high temperature operation thus requires more robust materials, assembly processes and higher reliability compare to consumer products. Deeper temperature cycles in use case requires higher board-level reliability. EPTC 2016 have line up a keynote and an invited speakers to present on the automotive packaging.  Full details are in the subsequent pages. Download speakers line up here


In 2015, China imported nearly 70% of the world’s chips with about $230 billion dollars, which is more than the spend on crude oil. To change this situation, several plans, e.g. “Made in China 2025” (MIC 2025), were published by China’s State Council recently, to invest more than $100 billion in the semiconductor industry to reach its goal of playing a larger role in the global market. With the MIC 2025 plan, China is aiming to improve the self-sufficiency rate for ICs in the nation to 40% in 2020, and boost the rate further to 70% in 2025.

How these policies and investment will impact the current semiconductor industry? What’s the Opportunities & Challenges for the packaging community? EPTC has set up a panel session to explore the answers: “Rise of China Semiconductor”. There are also invited presentations to demonstrate current state-of-art of advanced packaging development in China. Download speakers line up here




The Internet of Things (IoT) is the network of physical objects or “things” embedded with electronics, software, sensors, and network connectivity, which enables these objects to collect and exchange data. The size and cost of electronic components that are needed to support capabilities such as sensing, tracking and control mechanisms, play a critical role in the widespread adoption of IOT for various industry applications.  EPTC 2016 has lined up a keynote speaker, 2 PDC courses, and series of invited papers & presentations to present on the internet of things from packaging perspective. Full details are in the subsequent pages. Download speakers lineup here.



The mobile market is accelerating demand for more compact and complex semiconductor packages that are challenging traditional packaging technology in the areas of form factor, reliability and performance. This demand is driving the quick growth of conventional Fan-In wafer level packages (WLP), with estimated CAGR of 9% from 2014 to 2019. In another respect, the demand for high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous is driving the growth of new Fan-Out WLP, which is projected at CAGR of 87% from 2015 to 2020(from Techsearch)!

EPTC 2016 has lined up short courses on Fan-In Fan-Out WLP Packaging and 2 invited speakers to present on the advanced Fan-Out WLP. Full details are in the subsequent pages. Download speakers line up here



Heterogeneous Integration Roadmap Workshop, December 2nd, 2016

Heterogeneous Integration Roadmap Workshop

Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. We now face new challenges with the slowing of Moore’s Law, the migration o to the Cloud, smart devices everywhere, and Internet of Things to Inbternet of Everything. While the pace of innovation is increasing to meet these challenges, the crucial question is will be the winning directions going forward?

The Heterogeneous Integration Roadmap (HIR), initialed by the IEEE CPMT Society ,and joined with IEEE EDS and Photonics Socidties and SEMI, will follow directly the purpose, process and format of the ITRS Heterogeneous Integration Roadmap (last ITRS 2.0 edition published on July 8th 2016)  for the 15-year assessment of  future requirements. This Heterogeneous Integration Roadmap  will continue the ITRS Heterogeneous Integration and Assembly and Packaging roadmapping workshops held in previous years at ESTC and other CPMT Conferences, while expanding the vision to address the major changes in the market place, and the disruptive changes in technology and the industry.   We invite  EPTC participants to attend this important working session for our profession, our industry and our research community.

Instructor’s Biography


William Chen (Bill) currently holds the position of ASE Fellow and Senior Technical Advisor at ASE Group. Prior to joining ASE, he was the Director at the Institute of Materials Research & Engineering in Singapore. Bill retired from IBM Corporation after a career spanning over thirty years in various R&D and managerial positions. He has held adjunct and visiting faculty positions at Cornell University, Hong Kong University of Science and Technology, and Binghamton University. Bill is the chair of the newly formed Heterogeneous Integration Technology Roadmap for Semiconductors, an initiative addressing technologies for the IoT, IoE and cloud computing era,  jointly sponsored by IEEE CPMT, SEMI and EDS.  He also chairs SEMI’s Advanced Packaging Committee. In 2009, Bill received the InterPACK Excellence Award for his contributions, and in 2010, he was presented with the IEEE CPMT Society David Feldman Outstanding Contribution Award. He is a past President of the IEEE CPMT Society and he has been elected a Fellow of IEEE and a Fellow of ASME. Bill received B. Sc. from London University, M.Sc. from Brown University and Ph.D. from Cornell University.


Wilmer R. Bottoms, Ph.D

Dr.  Bottoms received a B.S. degree in Physics from Huntington College in Montgomery, Alabama in 1965, and a Ph.D in Solid State from Tulane University in New Orleans in 1969 and is currently Chairman of Third Millennium Test Solutions. He has worked as a faculty member in the department of electrical engineering at Princeton University, manager of Research and Development at Varian Associates, founding President of the Semiconductor Equipment Group of Varian Associates and general Partner of Patricof & Co. Ventures. He has served as Chairman and CEO of Several Companies both public and private.

Dr. Bottoms has also served in a number of Government Advisory positions including Chairman of the Board on Assessment for NIST and a member of the Technical Advisory Committee on export controls for the US Commerce Department.

Dr. Bottoms currently serves as:

  • Emeritus Member of the Board of Tulane University
  • Co-Chair of the Heterogeneous Integration Roadmap
  • Chairman of the SEMI’s Awards Committee
  • Chairman of the Packaging and Package Substrates Technical Working Group for INEMI
  • Member of the Board of MIT’s Microphotonic Center
  • Chairman of APMT
  • Chairman of Third Millennium Test Solutions


Download PDF version here

Wednesday, 30th November 2016

730-830hrs Registration
0830-1220hrs PDC 1 : Nanotechnologies for Microelectronics Packaging Applications PDC 2 : 3D Integrated Circuit Failure Analysis PDC 3 : Fan-In and Fan-Out in Wafer Level Packaging
MR300, Level 3 MR301, Level 3 MR302, Level 3
1220-1310hrs Lunch @ MR329
1310-1700hrs PDC 4 : Energy Efficient Thermal Management of Data Centers PDC 5 : Internet of Things (IoT) focusing on Wireless Sensors Network and Active RFID PDC 6 : 2.5D and 3D-Stacked Integrated Circuits
MR300, Level 3 MR301, Level 3 MR302, Level 3
1730-1900hrs Panel Speaker Presentation (Topic : Rise of China Semiconductor) @ MR 303-304, Level 3
1900-1930hrs Panel Q & A

Thursday, 1st December 2016

0730-0830hrs (60min) Registration @ Level 3(Secretariat Room)
0840hrs (10min) Welcome Speech (EPTC 2016 General Chair) @ MR331-332, Level 3 Mr Ranjan Rajoo
0840-0900hrs (20min) Opening Address @ MR331-332, Level 3 Jean M. TREWHELLA, IEEE CPMT President
0900-0930hrs (30min) Keynote address 1 @ MR331-332, Level 3 Tom Dolbear(AMD) : Packaging Matters
0930-1000hrs (30min) Keynote address 2 @ MR331-332, Level 3 Prof. Kanji Otsuka(Meisi Univ) : How to Feed Enough to Greedy IOT Monster
10:00-10:30 hr (30min) Coffee/Tea break @ Summit 2
1030-1100 hrs (30min) Keynote address 3 @ MR331-332, Level 3 Prof. Zhu Wenhui(Suzhou Speed Semiconductor Technology) : Advances of 3D Integration in China
1100-1130 hrs (30min) Keynote address 4 @ MR331-332, Level 3 Dr Bill Chen(ASE) : Innovation in SiP & Heterogeneous Integration
1130-1200 hrs (30min) Keynote address 5 @ MR331-332, Level 3 Jagadish CV(SSMC) : Achieving Automotive Quality Excellence : Zero Defect Performance – A foundry’s perspective
1200-1330hrs (90min) Lunch @ Summit 2
Luncheon Talk ( Jean Trewhella ) Presentation of EPTC 2015 Best Paper Awards
Presentation of IEEE CPMT Certification of Appreciation to EPTC 2016 Organizing Committee
1330-1400hrs (30min) Advanced MIS SIP technology Mr. YB Lin, JCET What’s happening in TSV based 3D/2.5D IC packaging: Latest market & technology trends Mr. Santosh Kumar, Yole Development Overview of latest assembly equipment developments for advanced packaging Bob Chylak, K&S Chip Integrated Single Phase Liquid Cooling Using Pin Fin Enhanced Microgaps Prof. Yogendra Joshi, Georgia Tech A Novel NanoCopper-Based Advanced Packaging Material Dr. Zinn, Alfred A Lockheed Martin Space Systems Company Innovations in Packaging will enable the IoT world of the Future Dr. Bill Bottoms, 3MTS
MR331 MR332 MR333 MR334 MR335 MR336
1400-1520hrs (80min) Session A1 Session A2 Session A3 Session A4 Session A5 Session A6
1 (20min) Paper ID : 26 Paper ID : 36 Paper ID : 15 Paper ID : 06 Paper ID : 58 Paper ID : 19
2 (20min) Paper ID : 08 Paper ID : 52 Paper ID : 170 Paper ID : 11 Paper ID : 59 Paper ID : 21
3 (20min) Paper ID : 25 Paper ID : 89 Paper ID : 41 Paper ID : 12 Paper ID : 127 Paper ID : 28
4 (20min) Paper ID : 07 Paper ID : 88 Paper ID : 47 Paper ID : 17 Paper ID : 80 Paper ID : 45
Room MR331 MR332 MR333 MR334 MR335 MR336
1520-1630hrs (70min) Coffee/Tea Break/ Exhibitor Presentation @ Summit 2

Lam Research : Partnering for Growth in Advanced Packaging, Mr. Lee Chee Ping

Indium Corporation : Materials for Advance Packaging, Ms. Sze Pei LIM

PacTech Asia Sdn. Bhd : PacTech Technology Introduction (commercial video)

SPIL : SPIL Innovative Package Solutions, Mr. Albert Lan

AMAT : Process and Equipment Technology for Advanced Packaging, Dr. Arvind SUNDARRAJAN

ASM : Solutions For Large Format Packaging, Mr. Eugene Wee

1630-1750hrs (80min) Session B1 Session B2 Session B3 Session B4 Session B5 Session B6
1 (20min) Paper ID : 16 Paper ID : 48 Paper ID : 09 Paper ID : 18 Paper ID : 63 Paper ID : 44
2 (20min) Paper ID : 38 Paper ID : 50 Paper ID : 74 Paper ID : 24 Paper ID : 75 Paper ID : 95
3 (20min) Paper ID : 43 Paper ID : 86 Paper ID : 161 Paper ID : 46 Paper ID : 107 Paper ID : 103
4 (20min) Paper ID : 65 Paper ID : 93 Paper ID : 134 Paper ID : 106 Paper ID : 112
Room MR331 MR332 MR333 MR334 MR335 MR336
1830-2230hrs Conference Banquet ( Venue : Prive@ CHIJMES )

Friday, 2nd December 2016

0830-0900hrs (30min) IOT: Constraints and Requirements for Packaging Technology Dr. Sebastien Gallois-garreignot, STM Laser Processing of Printed Copper Interconnects On Polymer Substrates Dr. David HUTT. Loughborough Univ. Package Miniaturization & Integration for Future Automotive Applications Mr. Andreas Fischer, Robert Bosch Packaging and Testing of High Speed Rotor for MEMS Gas Turbine Engines Prof. Xiaojun Yan, Beihang Univ. Technology and Market Trends in Packaging Mr. Damo Srinivas, Lam Research Wafer Bonding as an Enabler for Microsystems Packaging and Integration Prof. Tan Chuan Seng, NTU
Room MR331 MR332 MR333 MR334 MR335 MR336
0900-1000hrs (60min) Session C1 Session C2 Session C3 Session C4 Session C5 Session C6
1 (20min) Paper ID : 70 Paper ID : 82 Paper ID : 13 Paper ID : 85 Paper ID : 147 Paper ID : 117
2 (20min) Paper ID : 102 Paper ID : 108 Paper ID : 72 Paper ID : 143 Paper ID : 218 Paper ID : 221
3 (20min) Paper ID : 142 Paper ID : 61 Paper ID : 137 Paper ID : 145
Room MR331 MR332 MR333 MR334 MR335 MR336
1000-1110hrs (70min) Coffee/Tea Break/ Exhibition@ Summit 2


Advisian : Realistic Simulation and Infinite Opportunities, Mr. Nishant Kumar

CST : Signal and Power Integrity Simulations in Packages and PCBs, Mr. Klaus Krohne Ulvac :

Nordson : X-ray Metrology “Measuring the Invisible”, Steve Hursey

CAD-IT : ANSYS Multiphysics Simulation for IoT, Dr. Lee Yong Jiun

AGC Asia Pacific Pte Ltd : “We are AGC !”, Ms. Jasmine Cheh

1110-1230hrs (80min) Session D1 Session D2 Session D3 Session D4 Session D5 Session D6
1 (20min) Paper ID : 201 Paper ID : 54 Paper ID : 55 Paper ID : 164 Paper ID : 144 Paper ID : 57
2 (20min) Paper ID : 236 Paper ID : 104 Paper ID : 56 Paper ID : 167 Paper ID : 180 Paper ID : 64
3 (20min) Paper ID : 33 Paper ID : 116 Paper ID : 100 Paper ID : 71 Paper ID : 209 Paper ID : 76
4 (20min) Paper ID : 35 Paper ID : 120 Paper ID : 125 Paper ID : 173 Paper ID : 119 Paper ID : 101
Room MR331 MR332 MR333 MR334 MR335 MR336
1230-1340 hrs (70min) Lunch @ Summit 2
Presentation of Appreciation to Invited Papers’ Authors
18th Electronic Packaging Technology Conference Organisation Committee Appreciation
19th Electronic Packaging Technology Conference Introduction
1340-1410hrs (30min) Enabling Design for Reliability in Advanced Interconnects for 3D IC and Next Generation Solar PV (Photovoltaics) Systems Prof. Arief Budiman, SUTD Multi-die integration using advanced fan-out packaging technology Mr. WonChul Do, Amkor Materials and Processes of Fan-out Wafer/Panel Level Packaging Dr. Li Ming, ASM 3D-PRINTING AND ELECTRONIC PACKAGING: CURRENT STATUS AND FUTURE CHALLENGES Prof. Christopher Bailey, University of Greenwich Patent MonetizationMr. Dexter Chin, Horizon IP Pte Ltd Advanced Devices Packaging Technologies for High Dense Power Converter in More Electric Aircraft Application Dr. Rejeki Simanjorang, Rolls Royce
Room MR331 MR332 MR333 MR334 MR335 MR336
1410 – 1530 hrs (80 min) Session E1 Session E2 Session E3 Session E4 Session E5 Session E6
1 (20min) Paper ID : 129 Paper ID : 122 Paper ID : 157 Paper ID : 78 Paper ID : 224 Paper ID : 136
2 (20min) Paper ID : 133 Paper ID : 156 Paper ID : 160 Paper ID : 178 Paper ID : 96 Paper ID : 158
3 (20min) Paper ID : 211 Paper ID : 185 Paper ID : 225 Paper ID : 190 Paper ID : 223 Paper ID : 184
4 (20min) Paper ID : 148 Paper ID : 212 Paper ID : 237 Paper ID : 188 Paper ID : 227
Room MR331 MR332 MR333 MR334 MR335 MR336
1530-1600hrs (30min) Coffee/Tea Break/ Exhibition@ Summit 2
1600-1720hrs (80 min) Session F1 Session F2 Session F3 Session F4 Session F5 IEEE CPMT PKG Roadmap Workshop
1 (20min) Paper ID : 194 Paper ID : 195 Paper ID : 172 Paper ID: 140 Paper ID : 66
2 (20min) Paper ID : 202 Paper ID : 233 Paper ID : 111 Paper ID: 99 Paper ID : 114
3 (20min) Paper ID : 208 Paper ID : 205 Paper ID : 189 Paper ID: 200 Paper ID : 109
4 (20min) Paper ID : 168 Paper ID : 191 Paper ID : 135 Paper ID: 146
Room MR332 MR333 MR334 MR335 MR336 MR331
1720-1750 hrs (30min) Keynote address 6 @ Summit 2 Prof. Ricky SW Lee, Hong Kong Univ. Science & Technology : Light-Emitting Diodes for Non-Lighting Applications ~ beyond seeing and being seen ~
1750-1810 (20min) Closing Ceremony and Lucky Draw @ Summit 2

Saturday, 3rd December 2016

SUTD(Singapore University of Technology and Design) Visit to ( 3D fabrication lab / International Design Centre / Jackie Chan Ancient Chinese Structures)


No. Room Program
1 MR331 Keynote / Technical Track 1
2 MR332 Keynote / Technical Track 2
3 MR333 Technical Track 3
4 MR334 Technical Track 4
5 MR335 Technical Track 5
6 MR336 Technical Track 6
7 Foyer 5 Exhibition & Registration
8 MR330 Conference Secretariat
9 MR329 PDC lunch
10 Summit 2 Conference Luncheon
11 MR300 PDC1 & PDC4
12 MR301 PDC2 & PDC5
13 MR302 PDC3 & PDC6
14 MR303-304 Panel session

EPTC 2016 Professional Development Course

Course Leader: James E. Morris
Title : Nanotechnologies for Microelectronics Packaging Applications:
Current trends in IoT, Wearable, 3D, Flex Circuits, Thermal and Embedded passives
Affiliation: James E. Morris, Portland State University, USA
Course description:




Course Leader: Ingrid De Wolf, Prof.
Title : 3D Integrated Circuits Failure Analysis
Affiliation: IMEC, Belgium & KULeuven, Belgium
Course description:





Course Leader: Albert Lan
Title : Fan-In and Fan-Out in Wafer Level Packaging
Affiliation: SPIL, Taiwan
Course description:



Course Leader: Yogendra Joshi
Title : Energy Efficient Thermal Management of Data Centers
Affiliation: Georgia Tech, USA
Course description:




Course Leader: Holden Li
Title : Internet of Things (IoT) focusing on Wireless Sensors Network and Active RFID
Affiliation: Tamasek Laboratories at Nanyang Technological University, Singapore
Course description:





Course Leader: Paul D. Franzon
Title : 2.5D- and 3D-Stacked Integrated Circuits
Affiliation: North Carolina State University, USA
Course description:




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