Seung Wook Yoon: Advanced eWLB FOWLP SiP Technology

Title : Advanced eWLB FOWLP SiP Technology DSC_5499_1335_Yoon_Seung_Wook_web
Invited Presentation: Seung Wook Yoon, Ph D. MBA
Affiliation: Director / Products & Technology Marketing, STATS ChipPAC Ltd.JCET Group, Singapore

 

 

The number of WLCSP (Wafer Level Packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design as well as its cost advantage. And it is also attractive to WE (wearable electronics) and IoT(Internet of Things) products.  The implications of these market drivers on the packaging are; higher performance designs, lower power consumption, lower cost, smaller form factor, thinner profile and higher level of integration.

eWLB (Embedded Wafer Level BGA) is one of key advanced packages because of advantages of higher I/O density, process easiness and integration flexibilities.  It also facilitates integration of multiple dies in one package without using substrates. eWLB provides smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield.

This paper introduces eWLB (embedded Wafer Level Ball Grid Array) /FO-WLP (fanout –WLP) for its current market and future trend&requirement, advantages, improved and advanced features and performance as well as reliability. This paper also discusses the wide range of FOWLP/eWLB adoptions in industry past years and novel features available for emerging market of IoT and WE. This advanced technology is well designed for 3D PoP, MEMS/sensors, 3D SiP modules as well as ultra-thin, highly integrated packaging solutions. Innovative FOWLP/eWLB features are also introduced with the merits and thermal/electrical characterization data as well as enhanced reliability.

 

Biography

Dr. YOON is currently in charge of Wafer Level Products & Technology Marketing in STATS ChipPAC PTE LTD.  His major interests are for wafer level products including eWLB/Fanout WLP, WLCSP, IPD (integrated Passive Device), flipchip bumping, TSV (Through Silicon Via), SiP and integrated 3D IC packaging.

Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR (Agency of Singapore Technology and Research), Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 25 US patents on microelectronic materials and electronic packaging. Currently contributing as technical committee member of prestigious international conferences, such as EPTC, ESTC, iMAPS, IWLPC and SEMI.