|Title : Multi-die integration using advanced fan-out packaging technology|
|Invited Presentation: WonChul Do|
The ability to integrate multiple die, passives components, and even packages is one of the key enablers for the widespread adoption of Fan-Out Wafer Level Package (FO-WLP). The other restrictions or challenges of traditional FO-WLP are limited line and space capabilities, creation of 3D structures, and good die scrapping concerns associated with chip first flow. Chip last and RDL first fan-out approach can overcome many of the issues associated with conventional fan-out technology and provide increased I/O and circuit density within a reduced footprint and profile. This presentation describes the process flow of a new chip last high density fan-out technology and compares its package capabilities with flip chip based 3D PoP at 15 mm package size. The results show the new chip last FO-WLP has better electrical and thermal performance with very robust component and board level reliability. More complicated SiP and its further miniaturization can be realized because RDL formation is done without any mold compound before chip attach is performed and the creation of advanced 3D structures and integration of passives with various surface finishes are possible. For the most aggressive designs such as interconnect for split die architecture or for High Bandwidth Memory (HBM), 2.5D interposer with fine line damascene Cu BEOL must be incorporated. For high performance and multi-die mobile products, FO-WLP with TSV-less interposer and chip last process flow can provide the 2.5D sub-micron routing capability, lowers cost, and improves electrical performances. The routing capability, process flow, and reliability results of a TSV-less package TV with 15 mm body will be presented.
WonChul Do is Sr. director of R&D Division Group and currently leading the development of next generation fan-out packaging technology at Amkor Technology Korea, Inc. He was package development project manager for 2.5D/TSV products until he took on the current role in 2014. He has more than 15 year experience in the semiconductor packaging field and has been involved in the development of flip chip package, wafer bumping and wafer level packaging and 2.5D/3D IC packaging. He received a Master of Science degree in Electronic Engineering from Sogang University in Seoul, Korea.