Lunchtime Talk : Jean Trewhella – Acceleration of Electronic Packaging Innovation through Collaboration

Acceleration of Electronic Packaging Innovation through Collaboration

JEAN M. TREWHELLA
IEEE CPMT President

 

photo_trewhella_2010As semiconductor scaling has slowed down making the cost per transistor increase the world has turned to packaging to lead the charge of innovation.   This is evident by the growth in packaging papers published per year at IEEE conferences and workshops. They have increased over 3X in past 20 years with over 3800 publications in 2015 alone!  Packaging innovation papers are not only being seen in the traditional packaging forums sponsored by the IEEE CPMT but they are cropping up in many of the hardware societies.  The CPMT Society recognizes this and we are driving collaboration across societies, and organizations to provide a comprehensive Heterogeneous Integration Roadmap to be used by the industry at large.

Why is packaging growing so rapidly?   We are seeing the demands increasing with the fruition of the Internet of Things (IOT).  All areas of Packaging covered by CPMT will be called on to collaborate to drive the required electronic packaging innovations. The sensors themselves require new materials and reliability solutions meet the challenges of new harsh environments. Compute power and massive storage needs will drive new packaging advances to support localized low cost, low power processors for data analysis as well the other extreme requirements of the highly secure high power central processing hubs. IOT interconnects with their ever increasing bandwidth and latency requirements will call on innovations in signal and power integrity for wired and wireless connections. Assembly manufacturing advances are needed to address a much broader set of components including optical, electronic, actives, passives, and antennas which need to be tightly integrated.  Time to market is key and thus modeling and simulation will be called on to predict the thermal and mechanical resilience of the required hybrid solutions.

As the Packaging Society for IEEE, we welcome you to join CPMT as we strive to support the collaboration of technical communities through the exchange of ideas during this exciting time of exploration!

 

Bio JEAN M. TREWHELLA 

Ms. Trewhella received her B.S. in Physics from Antioch College (1987) and her M.S. in Applied Physics from Columbia University (1992). She joined the T.J. Watson Research Center, IBM, in 1988 where her work included polymer optical waveguides fabrication, electrical modeling, and opto-mechanical package design for data communication systems. In 2000 she created the High Speed Electrical and Optical Packaging Group in IBM Research directing work in electrical link signal integrity,  advanced 1st and 2nd level packaging, and low cost high speed opto-mechanical packaging. She received an Outstanding Technical Achievement Award for her work on 10Gbps Ethernet Transceiver Development in 2003. In 2005 she drove IBM wide team of engineers and scientists to highlight key disruptive technologies synthesizing the messages into three GTO topics: Technology, Application-Optimized Systems, and Services 2.0.  From 2006-2008 she was responsible for the Electronic Packaging Integration Group in IBM STG where her team developed the power5 and z10 system hardware. Currently Jean Trewhella is the Director of IBM Packaging Research and Development Center with responsibility of 3D, low cost, and high performance packaging technology for current and future products.

Ms. Trewhella was on the Strategic Advisory Board for NSF STC – Materials & Devices for Information Technology Research 2004-2008, she served as the General Chair of the 60th ECTC and is currently a member at large of the CPMT Board of Governors. She has authored numerous papers and holds over 20 US patents.

EPTC 2016: Speaker Update, Dr Rejeki Simanjorang will talk about Advance Packaging Requirement for Power Semiconductor Module

Dr Rejeki Simanjorang will talk about: Requirement for Advanced-Packaging Technology of Power Semiconductor Module in High Power Density Converter for More Electric Transportation. His presentation will elaborate the electrical performances of power module required for high speed switching in high power density converter. Parasitic impedance in power module that originates from devices and packaging layout will be discussed. Their effects to the power converters such as overshoot voltage, EMI issues, and switching loss will be elaborated. Finally, advanced packaging technique to minimize these parasitic impedances will be presented. More detail description can be found here

 

EPTC 2016: Speaker Update, Bob Chylak will talk about Opportunities and Challenges for Advance Packaging Equipment

Bob Chylak (K&S) will talk about: Opportunities and Challenges for Advance Packaging Equipment. The multitude of packaging processes creates both challenges and opportunities for equipment suppliers. The opportunities are of course to sell equipment for these emerging markets. But there is also risk of developing machines for markets that then don’t materialize in a good ROI. The end-users of the equipment are challenged with trying to develop innovative packaging solutions that distinguish themselves from their competitors without requiring equipment that is so customized that cost become prohibitive. The logical path for equipment suppliers is to develop highly versatile and re-configurable machines. This effort can be helped by the end users being careful to not over-spec the requirements, aiming for as much standardization as possible without limiting their competitive advantages and close collaboration between equipment suppliers and users. Further detail for Bob’s talk and bio can be found here