| Title :Wafer Bonding as an Enabler for Microsystems Packaging and Integration |  |
| Invited Presentation: Chuan Seng Tan | |
| Affiliation: Nanyang Technological University, Singapore |
Wafer bonding has come a long way in semiconductor manufacturing. Broadly, it can be classified as direct or indirect bonding. With the emergence of 3D packaging, MEMS packaging, engineered substrate and monolithic integration, wafer bonding has increasingly played a pivotal role. In the first half of this talk, solderless copper bonding is discussed with emphasis on surface passivation with self-assembled monolayer and surface activation with inert plasma. Recent work on copper nano-particles and micro-particles mixture for die attach application is also discussed. A demonstration of TSV-less CMOS-MEMS stacking with metal bonding is showcased. In the second half of this talk, discussion on molecular bonding of silicon and non-silicon materials is discussed. Applications in engineered substrate and monolithic integration using molecular bonding are also presented.
Biography
Chuan Seng Tan received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In February 2014, he was promoted to the rank of Associate Professor (with tenure). His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs) as well as engineered substrate for electronics-photonics integration. He authored and edited four books. He is an associate editor for Elsevier Microelectronics Journal (MEJ). He is a member of IEEE.
Electronics Packaging Technology Conference 