Yogendra Joshi: Chip Integrated Single Phase Liquid Cooling Using Pin Fin Enhanced Microgaps

Title :Chip Integrated Single Phase Liquid Cooling Using Pin Fin Enhanced Microgaps Picture1
Invited Presentation: Yogendra Joshi
Affiliation: G.W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332


High performance planar and three-dimensional (3D) stacked chip microsystems of the future have been projected to result in background heat fluxes in excess of 1 kW/cm2, and localized hot spots of 5 kW/cm2 or more.  Requirements for routing of electrical interconnects across the entire 3D chip stack, along with the need for enhancement of heat transfer surface area have made microgaps incorporating pin fin arrays an attractive design configuration.  Liquid cooling using microgaps is also of interest in ultraportable applications, where increasing chip leakage power is becoming a serious limitation. In this talk, I will discuss the design evolution of a single phase liquid cooled chip integrated package to handle large background heat fluxes, along with localized hot spots.  I will start by addressing the flow delivery plenum design to insure structural reliability, along with uniform flow distribution.  Experimental and computational studies of single phase forced convection in enhanced microgaps to handle highly non-uniform power maps will be presented.  The effectiveness of pin clustering to handle non-uniform heat fluxes within the microgap will be demonstrated. Finally, examples of single phase microfluidic cooling for chip cooling applications will be presented.



Yogendra Joshi is Professor and John M. McKenney and Warren D. Shiver Distinguished Chair at the G.W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology.  At Georgia Tech he is the Principal Investigator of the Office of Naval Research Consortium for Resource-Secure Outposts (CORSO), and Site Director for the National Science Foundation Industry/University Cooperative Research Center on Energy Efficient Electronic Systems.  His research interests are in multi-scale thermal management.  He received a Ph.D. in Mechanical Engineering and Applied Mechanics, from the University of Pennsylvania in 1984.  He is an elected Fellow of the ASME, the American Association for the Advancement of Science, and IEEE. He was a co-recipient of ASME Curriculum Innovation Award (1999), Inventor Recognition Award from the Semiconductor Research Corporation (2001), the ASME Electronic and Photonic Packaging Division Outstanding Contribution Award in Thermal Management (2006), ASME J. of Electronics Packaging Best Paper of the Year Award (2008), IBM Faculty Award (2008), IEEE SemiTherm Significant Contributor Award (2009), IIT Kanpur Distinguished Alumnus Award (2011), ASME InterPack Achievement Award (2011), ITherm Achievement Award (2012), and ASME Heat Transfer Memorial Award (2013).