|Title :Opportunities and Challenges for Advance Packaging Equipment.|
|Invited Presentation: Bob Chylak.|
|Affiliation: Kulicke and Soffa Industries, Inc.|
The slowdown of Moore’s Law chip scaling prompted a greater focus on packaging R&D over the last several years. These efforts have resulted in a proliferation of packaging solutions that are collectively referred to as Advanced Packaging. The new technologies are currently at various stages of the research-development-production path and it is not entirely clear which of these will emerge as the high volume manufacturing methods of the future. Only a few years ago 2.5D and 3D were thought so see huge volumes by now, but this has largely not materialized except for the case of advanced stacked memory and leading-edge graphics cards.
SiP and Fan-out Wafer Level Packaging (FOWLP) now appear as the highest projected growth rate packages in the electronics packaging space and their future as the leading high volume manufacturing technologies appears more certain. Part of the increasing demand for FOWLP is driven by the potential for high levels of integration, creating FOWLP SiP options that enable the smallest form factor, lowest cost and highest performance for new multi-die designs. The range of potential FOWLP packages goes from the low cost single die, with or without passives, to complex multi-die 3D packaged assemblies. But within this new packaging technology, there is a lack of standards resulting in multiple options that place very different requirements on the assembly equipment. These include face-up/face-down die placement, RDL last (die first)/RDL first (die last), local/global alignment. Depending on the particular methodology, the pick and place tools would need pulsed heated or constant heat bondheads, flip/unflip, high/low force, accuracy ranging from 3um to 10um and potentially the ability to place on organic substrates, wafers or panels. All of these options have throughput and COO implications. The assembly needs can be addressed with equipment architectures ranging from high-end TCB/flip chip bonders with high accuracy and lower UPH to high-end SMT tools with medium accuracy and very high UPH. There are also opportunities to integrate PC Board manufacturing and backend assembly.
Beyond fan-out, true thermocompression bonding such as for TSV memory stacks, high accuracy flip chip bonding to substrates or wafers and SMT-type placement of substrate-embedded die are all within the die placement equipment space.
The multitude of packaging processes creates both challenges and opportunities for equipment suppliers. The opportunities are of course to sell equipment for these emerging markets. But there is also risk of developing machines for markets that then don’t materialize in a good ROI. The end-users of the equipment are challenged with trying to develop innovative packaging solutions that distinguish themselves from their competitors without requiring equipment that is so customized that cost become prohibitive. The logical path for equipment suppliers is to develop highly versatile and re-configurable machines. This effort can be helped by the end users being careful to not over-spec the requirements, aiming for as much standardization as possible without limiting their competitive advantages and close collaboration between equipment suppliers and users.
About the speaker:
Bob Chylak is Vice President, Packaging and Process Integration for Kulicke & Soffa. He is responsible for the research and development of packaging solutions across all K&S products. Bob has more than 25 years of experience in the semiconductor industry. He has a BS-EE degree from Penn State University and completed Executive Management Studies at Stanford University. Bob has published more than 50 papers and holds numerous patents. He can be reached at firstname.lastname@example.org.