Albert Lan: Fan-In and Fan-Out in Wafer Level Packaging

Title : Fan-In and Fan-Out in Wafer Level Packaging spil_albert-lan.jpg
Course Leader: Albert Lan
Affiliation: Senior Director, Engineering Center, SPIL, Taiwan

Course description:

The Wafer Level Package (WLP) continues to see strong growth driven by mobile phones, tablets, portable players, wearable and IoT devices with its benefits of small form factor and low profile packages.

In this course, we will introduce the innovative solutions of WLP include mold type WLCSP (mWLCSP), Fan-out Wafer Level Package (FOWLP). Also, the future trend will be covered Panel Level FO technology.

Course Outline:

  1. Introduction
    • What is Wafer Level Package
    • Market Trend of Wafer Level Package
  2. Innovative Package Solutions Introduction and Challenge
    • Molded WLP (mWLCSP)
    • Fan-Out WLP (FOWLP)
  3. Future Package Solutions Introduction and Challenge
    • Panel Level Fan-Out (PLFO)
  4. Summary

About the speaker:

Education:

  • Master of industrial & mechanical engineering department, Univ. of Wisconsin, Madison

Job Experience:

  • Over 20 years of job experience on semiconductor industry, especially focus on bumping and flip chip advanced assembly technology.
  • Vice Chairman of Semiconductor Equipment and Materials International Taiwan Association.
  • Chairman of TILA (Taiwan Intelligent Leader Association)

Now :

  • Senior Director of Engineering Center of SPIL (Siliconware, Taiwan), which is 3rd biggest assembly house in the world now